MT16LSDT6464A Datasheet PDF - Micron Technology SYNCHRONOUS DRAM MODULE Specs

MT16LSDT6464A - SYNCHRONOUS DRAM MODULE

Datasheet Summary

Description

SYMBOL RAS#, CAS#, WE# CK0-CK3 TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.

Clock: CK is driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CK.

Features

PC100- and PC133-compliant.
JEDEC-standard 168-pin, dual in-line memory module (DIMM).
Unbuffered.
256MB (32 Meg x 64), 512MB (64 Meg x 64).
Single +3.3V ±0.3V power supply.
Fully synchronous; all signals registered on positive edge of system clock.
Internal pipelined operation; column address can be changed every clock cycle.
Internal SDRAM banks for hiding row access/precharge.
Programmable burst lengths: 1, 2, 4.

Datasheet Details

Part number	MT16LSDT6464A
Manufacturer	Micron Technology
File Size	658.63 KB
Description	SYNCHRONOUS DRAM MODULE
Datasheet	MT16LSDT6464A Datasheet
Additional preview pages of the MT16LSDT6464A datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com 256MB / 512MB (x64) 168-PIN SDRAM DIMMs SYNCHRONOUS DRAM MODULE Features • PC100- and PC133-compliant • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • Unbuffered • 256MB (32 Meg x 64), 512MB (64 Meg x 64) • Single +3.3V ±0.

Published: Dec 9, 2007 |